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1

[IEEE 2019 20th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2019.3.6-2019.3.7)] 20th International Symposium on Quality Electronic Design (ISQED) - Impact of Double-Row Height Standard Cells on Placement and Routing

Lin, Rung-Bin, Chiang, Yu-Xiang

Year:

2019

Language:

english

File:

PDF, 563 KB

english, 2019

2

Comments on "Filling algorithms and analyses for layout density control"

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2002

Language:

english

File:

PDF, 201 KB

english, 2002

3

[IEEE Sixth International Symposium on Quality of Electronic Design (ISQED'05) - San Jose, CA, USA (21-23 March 2005)] Sixth International Symposium on Quality of Electronic Design (ISQED'05) - Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers

Meng-Chiou Wu,, Rung-Bin Lin,

Year:

2005

Language:

english

File:

PDF, 757 KB

english, 2005

4

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - A Divide-and-Conquer Approach to Estimating Minimum/Maximum Leakage Current

Guang-Wan Liao,, Ja-Shong Feng,, Rung-Bin Lin,

Year:

2005

Language:

english

File:

PDF, 236 KB

english, 2005

5

[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - Is more redundancy better for on-chip bus encoding

Hsun-Chieh Yu,, Rung-Bin Lin,

Year:

2006

Language:

english

File:

PDF, 3.29 MB

english, 2006

6

FINDING DICING PLANS FOR MULTIPLE PROJECT WAFERS FABRICATED WITH SHUTTLE MASK

WU, MENG-CHIOU, LIN, RUNG-BIN

Journal:

Journal of Circuits System and Computers

Year:

2008

Language:

english

File:

PDF, 563 KB

english, 2008

7

[IEEE 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Bochum, Germany (2017.7.3-2017.7.5)] 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - On Benchmarking Pin Access for Nanotechnology Standard Cells

Fang, Shang-Rong, Tai, Cheng-Wei, Lin, Rung-Bin

Year:

2017

Language:

english

File:

PDF, 1.33 MB

english, 2017

8

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction

Lin, Kuen-Wey, Lin, Yeh-Sheng, Li, Yih-Lang, Lin, Rung-Bin

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2018

Language:

english

File:

PDF, 4.79 MB

english, 2018

9

[IEEE 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Hong Kong (2018.7.8-2018.7.11)] 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Designing and Benchmarking of Double-Row Height Standard Cells

Chiang, Yu-Xiang, Tai, Cheng-Wei, Fang, Shang-Rong, Peng, Kai-Chun, Chung, Yuan-Dar, Yang, Jin-Kai, Lin, Rung-Bin

Year:

2018

Language:

english

File:

PDF, 701 KB

english, 2018

10

Variable-sized object packing and its applications to instruction cache design

Journal:

Computers & Electrical Engineering

Year:

2008

Language:

english

File:

PDF, 211 KB

english, 2008

11

Conjugate conflict continuation graphs for multi-layer constrained via minimization

Rung-Bin Lin, Shu-Yu Chen

Journal:

Information Sciences

Year:

2007

Language:

english

File:

PDF, 311 KB

english, 2007

12

Combinatorial optimization by stochastic automata

Eugene Shragowitz, Rung-Bin Lin

Journal:

Annals of Operations Research

Year:

1990

Language:

english

File:

PDF, 1.69 MB

english, 1990

13

Pattern Run-Length for Test Data Compression

Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2012

Language:

english

File:

PDF, 1023 KB

english, 2012

14

Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2008

Language:

english

File:

PDF, 375 KB

english, 2008

15

[IEEE 2009 Asian Test Symposium - Taichung, Taiwan (2009.11.23-2009.11.26)] 2009 Asian Test Symposium - Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing

Lee, Lung-Jen, Tseng, Wang-Dauh, Lin, Rung-Bin, Yu, Chi-Wei

Year:

2009

Language:

english

File:

PDF, 509 KB

english, 2009

16

[IEEE 2013 14th International Symposium on Quality Electronic Design (ISQED 2013) - Santa Clara, CA (2013.3.4-2013.3.6)] International Symposium on Quality Electronic Design (ISQED) - Relocatable and resizable SRAM synthesis for via configurable structured ASIC

Hsin-Hung Liu,, Rung-Bin Lin,, I-Lun Tseng,

Year:

2013

Language:

english

File:

PDF, 3.16 MB

english, 2013

17

[IEEE Conference Publications Design Automation and Test in Europe - Grenoble, France (2013.03.18-2013.03.22)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 - Slack Budgeting and Slack to Length Converting for Multi-Bit Flip-Flop Merging

Lu, Chia-Chieh, Lin, Rung-Bin

Year:

2013

Language:

english

File:

PDF, 552 KB

english, 2013

18

[IEEE 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems - Krakow, Poland (2007.04.11-2007.04.13)] 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems - Reticle Exposure Plans for Multi-Project Wafers

Lin, Rung-Bin, Hsu, Da-Wei, Kuo, Ming-Hsine, Wu, Meng-Chiou

Year:

2007

Language:

english

File:

PDF, 304 KB

english, 2007

19

[IEEE 2013 2nd International Symposium on Next-Generation Electronics (ISNE 2013) - Kaohsiung (2013.2.25-2013.2.26)] 2013 International Symposium on Next-Generation Electronics - Via-configurable structured ASIC implementation of OpenRISC 1200 based SoC platform

Tsung-Han Heish,, Rung-Bin Lin,

Year:

2013

Language:

english

File:

PDF, 1.73 MB

english, 2013

20

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Benchmark circuits improve the quality of a standard cell library

Rung-Bin Lin,, Isaac Shuo-Hsiu Chou,, Chi-Ming Tsai,

Year:

1999

Language:

english

File:

PDF, 414 KB

english, 1999

21

[IEEE Comput. Soc 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India (4-8 Jan. 2003)] 16th International Conference on VLSI Design, 2003. Proceedings. - A low power-delay product page-based address bus coding method

Chi-Ming Tsai,, Guang-Wan Liao,, Rung-Bin Lin,

Year:

2003

Language:

english

File:

PDF, 321 KB

english, 2003

22

Fuzzy logic approach to VLSI placement

Kang, E.Q., Rung-Bin Lin,, Shragowitz, E.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

1994

Language:

english

File:

PDF, 1.23 MB

english, 1994

23

[IEEE 2008 IEEE Computer Society Annual Symposium on VLSI - Montpellier, France (2008.04.7-2008.04.9)] 2008 IEEE Computer Society Annual Symposium on VLSI - Standard Cell Like Via-Configurable Logic Block for Structured ASICs

Li, Mei-Chen, Tung, Hui-Hsiang, Lai, Chien-Chung, Lin, Rung-Bin

Year:

2008

Language:

english

File:

PDF, 796 KB

english, 2008

24

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Low power CMOS off-chip drivers with slew-rate difference

Rung-Bin Lin,, Jinq-Chang Chen,

Year:

1999

Language:

english

File:

PDF, 426 KB

english, 1999

25

[IEEE 2009 Asian Test Symposium - Taichung, Taiwan (2009.11.23-2009.11.26)] 2009 Asian Test Symposium - A Multi-dimensional Pattern Run-Length Method for Test Data Compression

Lee, Lung-Jen, Tseng, Wang-Dauh, Lin, Rung-Bin, Lee, Chen-Lun

Year:

2009

Language:

english

File:

PDF, 453 KB

english, 2009

26

[IEEE 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - Dresden (2010.03.8-2010.03.12)] 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - Power gating design for standard-cell-like structured ASICs

Sin-Yu Chen,, Rung-Bin Lin,, Hui-Hsiang Tung,, Kuen-Wey Lin,

Year:

2010

Language:

english

File:

PDF, 590 KB

english, 2010

27

[IEEE 2009 IEEE Computer Society Annual Symposium on VLSI - Tampa, Florida, USA (2009.05.13-2009.05.15)] 2009 IEEE Computer Society Annual Symposium on VLSI - Context-aware Post Routing Redundant Via Insertion

Chu, Po-Heng, Lin, Rung-Bin, Hsu, Da-Wei, Chen, Yu-Hsing, Tseng, Wei-Chih

Year:

2009

Language:

english

File:

PDF, 358 KB

english, 2009

28

[IEEE Comput. Soc 7th Asia and South Pacific Design Automation Conference. 15h International Conference on VLSI Design - Bangalore, India (7-11 Jan. 2002)] Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design - Weight-based bus-invert coding for low-power applications

Rung-Bin Lin,, Chi-Ming Tsai,

Year:

2002

File:

PDF, 597 KB

2002

29

Reticle Design for Minimizing Multiproject Wafer Production Cost

Lin, Rung-Bin, Wu, Meng-Chiou, Tsai, Shih-Cheng

Journal:

IEEE Transactions on Automation Science and Engineering

Year:

2007

Language:

english

File:

PDF, 1.88 MB

english, 2007

30

[IEEE 2010 International Computer Symposium (ICS 2010) - Tainan, Taiwan (2010.12.16-2010.12.18)] 2010 International Computer Symposium (ICS2010) - Cascaded broadcasting for test data compression

Chang, Cheng-Ho, Lee, Lung-Jen, Tseng, Wang-Dauh, Lin, Rung-Bin

Year:

2010

Language:

english

File:

PDF, 353 KB

english, 2010

31

[IEEE 2010 International Computer Symposium (ICS 2010) - Tainan, Taiwan (2010.12.16-2010.12.18)] 2010 International Computer Symposium (ICS2010) - 2n Pattern run-length for test data compression

Chang, Cheng-Ho, Lee, Lung-Jen, Tseng, Wang-Dauh, Lin, Rung-Bin

Year:

2010

Language:

english

File:

PDF, 254 KB

english, 2010

32

[IEEE 2008 IEEE International Conference on Computer Design (ICCD) - Lake Tahoe, CA, USA (2008.10.12-2008.10.15)] 2008 IEEE International Conference on Computer Design - Router and cell library co-development for improving redundant via insertion at pins

Tseng, Wei-Chih, Chen, Yu-Hsing, Lin, Rung-Bin

Year:

2008

Language:

english

File:

PDF, 570 KB

english, 2008

33

[IEEE IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. Proceedings - Tianjin, China (4-6 Dec. 2000)] IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394) - A low power-delay-product multiplier with dynamic operand exchange

Chi-Ming Tsai,, Tsai-Min Chiang,, Chyi-Hui Hong,, Kun-Tien Kuo,, Rung-Bin Lin,

Year:

2000

Language:

english

File:

PDF, 381 KB

english, 2000

34

[IEEE Design, Automation & Test in Europe Conference - Nice, France (2007.04.16-2007.04.20)] 2007 Design, Automation & Test in Europe Conference & Exhibition - Double-Via-Driven Standard Cell Library Design

Lin, Tsai-Ying, Lin, Tsung-Han, Tung, Hui-Hsiang, Lin, Rung-Bin

Year:

2007

Language:

english

File:

PDF, 413 KB

english, 2007

35

[IEEE 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2009.04.28-2009.04.30)] 2009 International Symposium on VLSI Design, Automation and Test - Circuit acyclic clustering with input/output constraints and applications

Rung-Bin Lin,, Tsung-Han Lin,, Shin-An Wu,

Year:

2009

Language:

english

File:

PDF, 289 KB

english, 2009

36

[IEEE IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) - Tampa, FL, USA (11-12 May 2005)] IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) - A Comparative Study on Dicing of Multiple Project Wafers

Meng-Chiou Wu,, Rung-Bin Lin,

Year:

2005

Language:

english

File:

PDF, 71 KB

english, 2005

37

[IEEE 2010 11th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2010.03.22-2010.03.24)] 2010 11th International Symposium on Quality Electronic Design (ISQED) - Clock routing for structured ASICs with via-configurable fabrics

Rung-Bin Lin,, I-Wei Lee,, Wen-Hao Chen,

Year:

2010

Language:

english

File:

PDF, 712 KB

english, 2010

38

Reduction of power dissipation during scan testing by test vector ordering

Tseng, Wang-Dauh, Lee, Lung-Jen, Lin, Rung-Bin

Journal:

Journal of the Chinese Institute of Engineers

Year:

2010

Language:

english

File:

PDF, 456 KB

english, 2010

39

[IEEE Comput. Soc Eleventh International Conference on VLSI Design - Chennai, India (4-7 Jan. 1998)] Proceedings Eleventh International Conference on VLSI Design - A new statistical approach to timing analysis of VLSI circuits

Rung-Bin Lin,, Meng-Chiou Wu,

Year:

1998

Language:

english

File:

PDF, 721 KB

english, 1998

40

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Coupling Reduction Analysis of Bus-Invert Coding

Year:

2005

Language:

english

File:

PDF, 461 KB

english, 2005

41

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Multiple Project Wafers for Medium-Volume IC Production

Meng-Chiou Wu,, Rung-Bin Lin,

Year:

2005

Language:

english

File:

PDF, 215 KB

english, 2005

42

[IEEE 2006 International Symposium on VLSI Design, Automation and Test - Ambassador Hotel, Hsinchu (2006.4.26-2006.4.26)] 2006 International Symposium on VLSI Design, Automation and Test - Floorplanning Multiple Reticles for Multi-project Wafers

Wu, Meng-chiou, Tsai, Shr-cheng, Lin, Rung-bin

Year:

2006

Language:

english

File:

PDF, 3.50 MB

english, 2006

43

[IEEE 2007 International Symposium on VLSI Design, Automation and Test - Hsinchu, Taiwan (2007.04.25-2007.04.27)] 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Interleaving of Gate Sizing and Constructive Placement for Predictable Performance

Kim, Sungjae, Shragowitz, Eugene, Karypis, George, Lin, Rung-Bin

Year:

2007

Language:

english

File:

PDF, 3.37 MB

english, 2007

44

[IEEE 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) - Dresden (2012.03.12-2012.03.16)] 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Design and analysis of via-configurable routing fabrics for structured ASICs

Hsin-Pei Tsai,, Rung-Bin Lin,, Liang-Chi Lai,

Year:

2012

Language:

english

File:

PDF, 2.65 MB

english, 2012

45

[IEEE Asia and South Pacific Conference on Design Automation, 2006. - Yokohama, Japan (Jan. 24, 2006)] Asia and South Pacific Conference on Design Automation, 2006. - Microsoft Word - ASP-DAC-2006-ID1185-17-11-2005.doc

Rung-Bin Lin,, Meng-Chiou Wu,, Wei-Chiu Tseng,, Ming-Hsine Kuo,, Tsai-Ying Lin,, Shr-Cheng Tsai,

Year:

2006

Language:

english

File:

PDF, 260 KB

english, 2006

46

[IEEE 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Marseille, France (2014.12.7-2014.12.10)] 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Transition inversion coding with parity check for off-chip serial transmission

Zeng, Jian, Zhou, Jian-Yang, Lin, Rung-Bin

Year:

2014

Language:

english

File:

PDF, 259 KB

english, 2014

47

[ACM Press the 2006 conference - Yokohama, Japan (2006.01.24-2006.01.27)] Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - Design space exploration for minimizing multi-project wafer production cost

Lin, Rung-Bin, Wu, Meng-Chiou, Tseng, Wei-Chiu, Kuo, Ming-Hsine, Lin, Tsai-Ying, Tsai, Shr-Cheng

Year:

2006

Language:

english

File:

PDF, 161 KB

english, 2006

48

[ACM Press the 15th ACM Great Lakes symposium - Chicago, Illinois, USA (2005.04.17-2005.04.19)] Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05 - Reticle floorplanning of flexible chips for multi-project wafers

Wu, Meng-Chiou, Lin, Rung-Bin

Year:

2005

Language:

english

File:

PDF, 326 KB

english, 2005

49

[ACM Press the 21st edition of the great lakes symposium - Lausanne, Switzerland (2011.05.02-2011.05.04)] Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11 - Rover

Lai, Liang-Chi, Chang, Hsih-Hang, Lin, Rung-Bin

Year:

2011

Language:

english

File:

PDF, 1.64 MB

english, 2011

50

Chip placement in a reticle for multiple-project wafer fabrication

Wu, Meng-Chiou, Lin, Rung-Bin, Tsai, Shih-Cheng

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2008

Language:

english

File:

PDF, 1.91 MB

english, 2008

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